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BT8376EPF Datasheet(PDF) 293 Page - Synaptics Incorporated. |
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BT8376EPF Datasheet(HTML) 293 Page - Synaptics Incorporated. |
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293 / 323 page ![]() Bt8370/8375/8376 5.0 Electrical/Mechanical Specifications Fully Integrated T1/E1 Framer and Line Interface 5.6 System Bus Interface (SBI) Timing N8370DSE Conexant 5-19 Figure 5-16. SBI Timing—2048K Mode NOTE(S): 1. TSYNC/RSYNC represents frame (TFSYNC/RFSYNC) and multiframe (TMSYNC/RMSYNC) offset. 2. RINDO/TINDO programmed high or low on a per-time slot basis (SBCn; addr 0E0-0FF). 3. Multiple offset values shown for illustration, refer to OFFSET controls (addr 0D2-0D3, 0D5-0D6). 4. Rising edge outputs and falling edge inputs shown. Refer to Figure 5-19 for other edge combinations. 5. Transmit ABCD signalling on TSIGI is sampled only during low nibble. 6. Received ABCD signalling on RSIGO is repeated in both high and low nibbles. 7. X2CLK control bit located in SBI_CR (addr 0D0). 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 RSBCKI RPCMO RSIGO(6) TS0 TS1 TS2 TS31 RSYNCO(1) RSYNCI RSYNCO RSYNCI RSYNCO RSYNCI(1) Offset = 000 (TS0, Bit1)(3) Offset = 00B Offset = 0FF(3) RSYNCO RSYNCI RSYNCO RSYNCI Offset = 000(3) Offset = 00B RSBCKI Receive Transmit RINDO(2) SIGFRZ TSBCKI TPCMI TSIGI(5) TSYNCO(1) TSYNCI TSYNCO TSYNCI TSYNCO TSYNCI(1) TSYNCO TSYNCI TSYNCO TSYNCI TSBCKI TINDO(2) A B C D A B C D A B C D TSIG31 TSIG0 TSIG1 AB C D A B C D A B C D |
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