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TMS320C80GF Datasheet(PDF) 124 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 124 Page - Texas Instruments |
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124 / 171 page ![]() TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 121 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SDRAM read cycles (continued) DCAB Command DDIN DBEN D[63:0] W TRG / CAS DSF CAS / DQM[7:0] RAS A[31:0] RL STATUS[5:0] RETRY READY FAULT UTIME PS[3:0] BS[1:0] AS[2:0] CT[2:0] CLKOUT State READ D DCAB Cycle Type r1 r2 r3 r5 r6 col col col col col r1 c1 c2 c3 c4 c1 c2 c3 c4 c1 c2 c3 c4 c1 c2 c3 c4 Col Pipe 3 Col A Col B Col C Col D READ ACTV (Col B) Row Col A Col C (Col D) C B A Idle col PAC PAC AB A, B C, D CD 0 For Normal Read, 1 For PDPT Read Figure 98. SDRAM Burst-Length 2, 3 Cycle Latency Read-Cycle Timing |
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