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TMS320C80GF Datasheet(PDF) 126 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 126 Page - Texas Instruments |
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126 / 171 page  TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 123 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SDRAM write cycles Write cycles begin with an activate (ACTV) command to activate the bank and select the row. The TC outputs the column address and activates the TRG / CAS and W strobes for each write command. For burst-length 1 accesses, a write command can occur on each cycle. For burst-length 2 accesses, a write command can occur every two cycles. The TC drives data out on D[63:0] during each cycle of an active-write command and indicates valid bytes by driving the appropriate CAS / DQM strobes low. During peripheral device packet transfers, DBEN remains high and D[63:0] are placed in the high-impedance state so that the peripheral can drive data into the memories. For SDRAM write cycles, see Figure 100 and Figure 101. |
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