TMS320C80GF datasheet(130/171 Pages) TI

130 / 171 page

TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

127

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

SDRAM block-write cycles

Block-write cycles allow SVRAMs and SGRAMs to write a stored color value to multiple column locations in a

single access. Block-write cycles are similar to write cycles except that DSF is driven high to indicate a

block-write command. Because burst is not supported for block write, burst length 2 accesses generate a single

block-write every other clock cycle (see Figure 104 and Figure 105).

DCAB

Command

DDIN

DBEN

D[63:0]

TRG / CAS

DSF

CAS / DQM[7:0]

RAS

A[31:0]

STATUS[5:0]

RETRY

READY

FAULT

UTIME

PS[3:0]

BS[1:0]

AS[2:0]

CT[2:0]

CLKOUT

State

BLKW

Sel D

DCAB

col

Col Pipe

0,1

Col A

Col B

Col C

Col D

BLKW

ACTV

Col B

Col A

Col C

Col D

Sel C

Sel B

Sel A

Idle

col

rspin

Cycle Type

Row

PAC

BLKW

Figure 104. SDRAM Burst-Length 1 Block-Write Cycle Timing

TMS320C80GF Datasheet(PDF) 130 Page - Texas Instruments

TMS320C80GF Datasheet(HTML) 130 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL