TMS320C80GF datasheet(128/171 Pages) TI

128 / 171 page

TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

125

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

SDRAM write cycles (continued)

DCAB

Command

DDIN

DBEN

D[63:0]

TRG / CAS

DSF

CAS / DQM[7:0]

RAS

A[31:0]

STATUS[5:0]

RETRY

READY

FAULT

UTIME

PS[3:0]

BS[1:0]

AS[2:0]

CT[2:0]

CLKOUT

State

WRT

DCAB

col

Col Pipe

2, 3

Col A

Col B

Col C

Col D

WRT

ACTV

(Col B)

Col A

Col C

(Col D)

Idle

col

rspin

Cycle Type

Row

A, B

C, D

PAC

Figure 101. SDRAM Burst-Length 2 Write-Cycle Timing

special register set cycles

Special register set (SRS) cycles are used to program control registers within an SVRAM or SGRAM. The ’C80

only supports programming of the color register for use with block writes. The cycle is similar to a single burst

length 1 write cycle but DSF is driven high. The values output on the ’C80 address bits cause the color register

to be selected as shown in Figure 102 (see Figure 103).

TMS320C80GF Datasheet(PDF) 128 Page - Texas Instruments

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