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TMS320C80GF Datasheet(PDF) 127 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 127 Page - Texas Instruments |
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127 / 171 page ![]() TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 124 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SDRAM write cycles (continued) DCAB Command DDIN DBEN D[63:0] W TRG / CAS DSF CAS / DQM[7:0] RAS A[31:0] RL STATUS[5:0] RETRY READY FAULT UTIME PS[3:0] BS[1:0] AS[2:0] CT[2:0] CLKOUT State WRT D DCAB r1 r2 r3 r5 r6 col col col col col r1 c1 Col Pipe 0,1 Col A Col B Col C Col D WRT ACTV Col B Col A Col C Col D C B A Idle col AB CD rspin PAC PAC PAC PAC Cycle Type Row A C B D WRT WRT 0 For Normal Read, 1 For PDPT Read c1 c1 c1 Figure 100. SDRAM Burst-Length 1 Write-Cycle Timing |
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