TMS320C80GF datasheet(131/171 Pages) TI

131 / 171 page

TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

128

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

SDRAM block-write cycles (continued)

DCAB

Command

DDIN

DBEN

D[63:0]

TRG / CAS

DSF

CAS / DQM[7:0]

RAS

A[31:0]

STATUS[5:0]

RETRY

READY

FAULT

UTIME

PS[3:0]

BS[1:0]

AS[2:0]

CT[2:0]

CLKOUT

State

BLKW

DCAB

col

Col Pipe

2, 3

ColA

ColB

BLKW

ACTV

Col A

Col B

Sel B

Sel A

Idle

col

rspin

Cycle Type

Row

PAC

Figure 105. SDRAM Burst-Length 2 Block-Write Cycle Timing

SVRAM transfer cycles

The SVRAM read- and write-transfer cycles transfer data between the SVRAM memory-array and the serial

transfers resemble a standard read cycle. Write-and split-write transfers resemble a standard write cycle.

Because the ’C80’s TRG output is used as CAS, external logic must generate a TRG signal (by decoding

STATUS) to enable the SVRAM transfer cycle. The value output on A[31:0] at column time represents the SAM

tap point (see Figure 106 through Figure 113).

TMS320C80GF Datasheet(PDF) 131 Page - Texas Instruments

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