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TMS320C80GF Datasheet(PDF) 132 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 132 Page - Texas Instruments |
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132 / 171 page ![]() TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 129 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 SVRAM transfer cycles (continued) Command DDIN DBEN D[63:0] W TRG / CAS DSF CAS / DQM[7:0] RAS A[31:0] RL STATUS[5:0] RETRY READY FAULT UTIME PS[3:0] BS[1:0] AS[2:0] CT[2:0] CLKOUT State r1 col r3 r2 r1 000 Cycle Type DCAB Tap Pt. col r6 r5 DCAB PAC Row 0 For Full, 1 For Split RTR ACTV Col Pipe c3 c2 c1 Figure 106. SVRAM Burst-Length 1, 2 Cycle Latency Read-Transfer Cycle Timing |
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