TMS320C80GF datasheet(139/171 Pages) TI

139 / 171 page

TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

136

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

SVRAM transfer cycles (continued)

Command

DDIN

DBEN

D[63:0]

TRG / CAS

DSF

CAS / DQM[7:0]

RAS

A[31:0]

STATUS[5:0]

RETRY

READY

FAULT

UTIME

PS[3:0]

BS[1:0]

AS[2:0]

CT[2:0]

CLKOUT

State

col

01x

Cycle Type

DCAB

col

Idle

PAC

Row

0 For Full, 1 For Split

WTR

ACTV

DCAB

Tap Pt.

col

Col Pipe

Figure 113. SVRAM Burst-Length 2, Write-Transfer Cycle Timing

SDRAM refresh cycle

The SDRAM refresh cycle is performed when the TC receives an SDRAM-cycle timing input (CT=0xx) at the

start of a refresh cycle. The RAS and TRG / CAS outputs are driven low for one cycle to strobe a refresh

command (REFR) into the SDRAM. The refresh address is generated internal to the SDRAM. The ’C80 outputs

a 16-bit pseudo-address (used for refresh bank decode) on A[31:16] and drives A[15:0] low (see Figure 114).

TMS320C80GF Datasheet(PDF) 139 Page - Texas Instruments

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