TMS320C80GF datasheet(141/171 Pages) TI

141 / 171 page

TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

138

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• HOUSTON, TEXAS 77251–1443

host interface

The ’C80 contains a simple four-pin mechanism by which a host or another device can gain control of the ’C80

local memory bus. The HREQ input can be driven low by the host to request the ’C80’s bus. Once the TC has

completed the current memory access, it places the local bus (except CLKOUT) into a high-impedance state.

It then drives the HACK output low to indicate that the host device owns the bus and can drive it. The REQ[1:0]

outputs reflect the highest priority cycle request being received internally by the TC. The host can monitor these

outputs to determine if it needs to relinquish the local bus back to the ’C80 (see Table 37).

Table 37. TC Priority Cycles

REQ[1:0]

ASSOCIATED INTERNAL TC REQUEST

SRT, urgent refresh, XPT, or VCPT

Cache / DEA request, urgent packet transfer

High-priority packet transfer

Low-priority packet transfer, trickle refresh, idle

device reset

The TMS320C80 is reset when the RESET input is driven low. The ’C80 outputs immediately go into a

high-impedance state with the exception of CLKOUT, HACK, and REQ[1:0]. While RESET is low, all internal

registers are set to their default values and internal logic is reset.

On the rising edge of RESET, the state of UTIME is sampled to determine if big-endian (UTIME = 0) or

little-endian (UTIME = 1) operation is selected. Also on the rising edge of RESET, the state of HREQ is sampled

to determine if the master processor comes up running (HREQ = 0) or halted (HREQ = 1).

Once RESET is high, the ’C80 drives the high-impedance signals to their inactive values. The TC then performs

32 refresh cycles to initialize system memory. If, during initialization refresh, the TC receives an SDRAM cycle

timing code (CT = 0xx), it performs an SDRAM DCAB cycle and a MRS cycle to initialize the SDRAM, and then

continues the refresh cycles.

After completing initialization refresh, if the MP is running, the TC performs its instruction-cache-fill request to

fetch the cache block beginning at 0xFFFFFFC0. This block contains the starting MP instruction located at

0xFFFFFFF8. If the MP comes up halted, the instruction cache fill does not take place until the first occurrence

of an EINT3 interrupt to unhalt the MP.

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