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TMS320C80GF Datasheet(PDF) 144 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 144 Page - Texas Instruments |
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144 / 171 page ![]() TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 141 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 PARAMETER MEASUREMENT INFORMATION timing parameter symbology Timing parameter symbols used herein were created in accordance with JEDEC Standard 100-A. In order to shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: A A[31 : 0] RDY READY CAS CAS / DQM[7 : 0] RST RESET CFG AS[2:0], BS[1:0], CT[2:0], PS[3:0], UTIME RTY RETRY CKI CLKIN REQ REQ[1:0] CKO CLKOUT RL RL CMP RETRY, READY, FAULT RR READY, RETRY D D[63:0] SCK SCLK0, SCLK1 EIN EINT1, EINT2, EINT3, or EINTx TCK TCK EMU EMU0, EMU1 TDI TDI FCK FCLK0, FCLK1 TDO TDO HAK HACK TMS TMS HRQ HREQ TRS TRST LIN LINT4 UTM UTIME MID A[31:0], STATUS[5:0] SI HSYNC0, VSYNC0, CSYNC0, HSYNC1, VSYNC1, or CSYNC1 OUT A[31:0], CAS / DQM[7 : 0], D[63:0], DBEN, DDIN, DSF, RAS, RL, STATUS[5:0], TRG / CAS, W SY HSYNC0, VSYNC0, CSYNC0 / HBLNK0, CBLNK0 / VBLNK0, HSYNC1, VSYNC1, CSYNC1 / HBLNK1, CBLNK1 / VBLNK1, CAREA0, or CAREA1 RAS RAS XPT XPT[2:0] OR XPTx Lowercase subscripts and their meanings are: The following letters and symbols and their meanings are: a access time H High c cycle time (period) L Low d delay time V Valid h hold time Z High impedance su setup time X Unknown, changing, or don’t care level t transition time w pulse duration (width) general notes on timing parameters The period of the output clock (CLKOUT) is twice the period of the input clock (CLKIN), or 2 × tc(CKI). The half cycle time (tH) that appears in the following tables is one-half of the output clock period, or equal to the input clock period, tc(CKI). All output signals from the ’C80 (including CLKOUT) are derived from an internal clock such that all output transitions for a given half cycle occur with a minimum of skewing relative to each other. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, refer to the appropriate cycle description section of this data sheet. |
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