TMS320C80GF datasheet(148/171 Pages) TI

148 / 171 page

TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

145

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

local bus timing: cycle completion inputs (see Figure 122 and Figure 123)

The cycle completion inputs are sampled at the beginning of each row access at the start of the r3 state. The

READY input is also sampled at the start of the r6 state and during each column access (2 and 3 cyc/col

accesses only). The RETRY input is sampled on each CLKOUT falling edge following r3. The value

n as used

in the parameters represents the integral number of half cycles between the transitions of the two signals in

question.

’C80-40

’C80-50

’C80-60

UNIT

NO.

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

ta(MIDV-CMPV)

Access time, RETRY, READY, FAULT valid

after memory identification (A, STATUS)

valid

ntH–9

ntH–8

ntH–7

tsu(CMPV-CKOL)

Setup time, RETRY, READY, FAULT valid to

CLKOUT no longer high

8.0

7.5

th(CKOL-CMPV)

Hold time, RETRY, READY, FAULT valid

after CLKOUT low

1.2

ta(RASL-RRV)

Access time RETRY, READY valid from

RAS low

ntH–8

ntH–7.5

ta(RLL-RRV)

Access time, RETRY, READY valid from RL

low

ntH–8

ntH–7.5

ta(CASL RRV)

Access time, READY

valid from CAS low

2 cyc/col accesses

tH–13.5

tH–12

ta(CASL-RRV)

valid from CAS low

(non-usertime mode)

3 cyc/col accesses

2tH–9

2tH–8

2tH–7

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