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TMS320C80GF Datasheet(PDF) 146 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 146 Page - Texas Instruments |
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146 / 171 page  TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 143 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 device reset timing requirements (see Figure 120) NO. MIN MAX UNIT 9 t (RSTL) P lse d ration RESET lo Initial reset during power-up 6th ns 9 tw(RSTL) Pulse duration, RESET low Reset during active operation 6th ns 10 tsu(HRQL-RSTH) Setup time of HREQ low to RESET high to configure self-bootstrap mode 4th ns 11 th(RSTH-HRQL) Hold time, HREQ low after RESET high to configure self-bootstrap mode 0 ns 12 tsu(UTML-RSTH) Setup time of UTIME low to RESET high to configure big-endian operation 4th ns 13 th(RSTH-UTML) Hold time, UTIME low after RESET high to configure big-endian operation 0 ns UTIME HREQ RESET 9 10 11 13 12 Figure 120. Device-Reset Timing |
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