TMS320C80GF datasheet(143/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

140

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

PARAMETER MEASUREMENT INFORMATION

Tester Pin

Electronics

VLOAD

IOL

IOH

Output

Under

Test

Ω

Where:

IOL

2.0 mA (all outputs)

IOH

400

µA (all outputs)

VLOAD =

1.5 V

60 pF typical load circuit capacitance

Figure 115. Test Load Circuit

signal transition levels

TTL-output levels are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V.

Figure 116 shows the TTL-level outputs.

0.6 V

0.8 V

2 V

2.4 V

Figure 116. TTL-Level Outputs

TTL-output transition times are specified as follows:

D For a high-to-low transition, the level at which the output is said to be no longer high is 2 V, and the level

at which the output is said to be low is 0.8 V.

D For a low-to-high transition, the level at which the output is said to be no longer low is 0.8 V, and the level

at which the output is said to be high is 2 V.

Figure 117 shows the TTL-level inputs.

2 V

0.8 V

Figure 117. TTL-Level Inputs

TTL-compatible input transition times are specified as follows:

D For a high-to-low transition on an input signal, the level at which the input is said to be no longer high is

2 V, and the level at which the input is said to be low is 0.8 V.

D For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is

0.8 V, and the level at which the input is said to be high is 2 V.

TMS320C80GF Datasheet(PDF) 143 Page - Texas Instruments

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