 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TMS320C80GF Datasheet(PDF) 147 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TMS320C80GF Datasheet(HTML) 147 Page - Texas Instruments |
|
|
147 / 171 page  TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 144 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 local bus timing requirements: cycle configuration inputs (see Figure 121) The cycle configuration inputs are sampled at the beginning of each row access during the r2 state. The inputs typically are generated by a static decode of the A[31:0] and STATUS[5:0] outputs. NO. MIN MAX UNIT 14 tsu(CFGV-CKOH) Setup time, AS, BS, CT, PS, and UTIME valid to CLKOUT no longer low 8 ns 15 th(CKOH-CFGV) Hold time, AS, BS, CT, PS, and UTIME valid after CLKOUT high 2 ns 16 ta(MIDV-CFGV) Access time, AS, BS, CT, PS, and UTIME valid after memory identification (A, STATUS) valid 3tH – 10 ns Valid Valid Valid Valid Row Address Cycle Type Valid UTIME PS[3:0] CT[2:0] BS[1:0] AS[2:0] RL A[31:0] STATUS[5:0] CLKOUT tH tH tH tH tH tH 15 14 16 Figure 121. Local Bus Timing: Cycle Configuration Inputs |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
