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TMS320C80GF Datasheet(PDF) 152 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 152 Page - Texas Instruments |
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152 / 171 page  TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 149 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 general output signal characteristics over full range of operating conditions†(continued) NO PARAMETER ’C80-40 ’C80-50 ’C80-60 UNIT NO. PARAMETER MIN MAX MIN MAX MIN MAX UNIT 23 th(OUTV-CKOL) Hold time, CLKOUT high after output valid D[63:0] A[31:0], STATUS[5:0], CAS/DQM[7:0‡ DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W ntH–7 ntH–6.5 ntH–5.5 ntH–5.3 ntH–4.3 ntH–3.9 ntH–5.3 ntH–4.3 ntH–3.9 ns 24 th(OUTV-CKOH) Hold time, CLKOUT low after output valid D[63:0] A[31:0] STATUS[5:0], CAS/DQM[7:0]‡ DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W ntH–7 ntH–6.5 ntH–6.5 ntH–5.5 ntH–5.5 ntH–4.5 ntH–4.5 ntH–4.1 ntH–4 ntH–4 ntH–4.5 ntH–4.1 ns 25 th(CKOL-OUTV) Hold time, output valid after CLKOUT low ntH–5.5 ntH–5 ntH–5 ns 26 th(CKOH-OUTV) Hold time, output valid after CLKOUT high ntH–5.5 ntH–5 ntH–4 ns 27 th(OUTV-OUTV) Hold time, output valid after output valid D[63:0] A[31:0], STATUS[5:0], CAS/DQM[7:0]‡ DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W ntH–7 ntH–6.5 ntH–5.5 ntH–6.5 ntH–5.5 ntH–5 ntH–5.9 ntH–5.5 ntH–4.7 ns 28 td(CKOH-OUTV) Delay time, CLKOUT no longer low to output valid D[63:0] A[31:0], STATUS[5:0], CAS/DQM[7:0]‡ DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W ntH+7 ntH+6.5 ntH+5.5 ntH+6.5 ntH+5.5 ntH+5 ntH+5.9 ntH+5.5 ntH+4.7 ns 29 td(CKOL-OUTV) Delay time, CLKOUT no longer high to output valid D[63:0] A[31:0], STATUS[5:0], CAS/DQM[7:0]‡ DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W ntH+7 ntH+6.5 ntH+5.5 ntH+6.5 ntH+5.5 ntH+5 ntH+5.9 ntH+5.5 ntH+4.7 ns 30 td(OUTV-CKOH) Delay time, output no longer valid to CLKOUT high ntH+5.5 ntH+5 ntH+5 ns 31 td(OUTV-CKOL) Delay time, output no longer valid to CLKOUT low ntH+5.5 ntH+5 ntH+5 ns 32 td(OUTV-OUTV) Delay time, output no longer valid to output valid D[63:0] A[31:0], STATUS[5:0], CAS/DQM[7:0]‡ DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W ntH+7 ntH+6.5 ntH+5.5 ntH+6.5 ntH+5.5 ntH+5 ntH+6.1 ntH+5.5 ntH+5 ns † Tested across full voltage. Test temperature is selected by manufacturing test flow. Compliance across full temperature range is ensured by device characterization. ‡ Except for CAS/DQM[7:0] during non user-timed 2 cycle/column accesses |
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