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TMS320C80GF Datasheet(PDF) 156 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 156 Page - Texas Instruments |
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156 / 171 page  TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 153 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 external-interrupt timing The following description defines the timing of the edge-triggered interrupts EINT1 – EINT3 and the level triggered interrupt LINT4 (see Note 4). See Figure 127. NO. ’C80-40 ’C80-50 ’C80-60 UNIT MIN MAX MIN MAX 48 tw(EINL) Pulse duration, EINTx low† 6 6 ns 49 tsu(EINH-CKOH) Setup time, EINTx high before CLKOUT no longer low‡ 11.5 9.5 ns 50 tw(EINH) Pulse duration, EINTx high† 6 6 ns 51 tsu(LINL-CKOL) Setup time, LINT4 low before CLKOUT no longer high‡ 10 8 ns † This parameter is assured by characterization and is not tested. ‡ This parameter must only be met to ensure that the interrupt is recognized on the indicated cycle. NOTE 4: In order to assure recognition, LINT4 must remain low until cleared by the interrupt service routine. Interrupt Recognized CLKOUT EINTx LINT4 48 49 50 51 Figure 127. External-Interrupt Timing |
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