TMS320C80GF datasheet(158/171 Pages) TI

158 / 171 page

TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

155

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

host-interface timing (see Figure 130)

’C80-40

’C80-50

’C80-60

UNIT

NO.

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tsu(REQV-CKOH)

Setup time, REQ1 – REQ0 valid to CLKOUT no

longer low

tH – 7

tH – 5.5

th(CKOH-REQV)

Hold time, REQ1 – REQ0 valid after CLKOUT

high

tH – 7

tH – 5.5

th(HRQL-HAKL)

Hold time for HACK high after HREQ goes low†

4tH – 12

td(HAKL-OUTZ)

Delay time, HACK low

to output hi-Z‡

All signals except

D[63:0]

d(HAKL OUTZ)

to out ut hi-Z‡

D[63:0]

td(HRQH- HAKH)

Delay time, HREQ high to HACK no longer low

td(HAKH-OUTD)

Delay time, HACK high to outputs driven†

6tH

tsu(HRQL-CKOH)

Setup time, HREQ low to CLKOUT no longer

low (see Note 5)

10.5

8.5

† This parameter is a functional minimum assured by logic and is not tested.

‡ This parameter is assured by characterization and is not tested.

NOTE 5: Parameter must be met only to ensure HREQ recognition during the indicated clock cycle.

TMS320C80GF Datasheet(PDF) 158 Page - Texas Instruments

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