TMS320C80GF datasheet(161/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

158

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

video interface timing: FCLK input and video outputs (see Note 6 and Figure 132)

NO.

MIN

MAX

UNIT

tc(FCK)

FCLK period

tw(FCKH)

Pulse duration, FCLK high

tw(FCKL)

Pulse duration, FCLK low

tt(FCK)

Transition time, FCLK (rise and fall)†

th(FCKL-SYL)

Hold time, HSYNC, VSYNC, CSYNC / HBLNK, CBLNK / VBLNK, or CAREA high after

FCLK low

th(FCKL-SYH)

Hold time, HSYNC, VSYNC, CSYNC / HBLNK, CBLNK / VBLNK, or CAREA low after FCLK

low

td(FCKL-SYL)

Delay time, FCLK no longer high to HSYNC, VSYNC, CSYNC / HBLNK, CBLNK / VBLNK,

or CAREA low

td(FCKL-SYH)

Delay time, FCLK no longer high to HSYNC, VSYNC, CSYNC / HBLNK, CBLNK / VBLNK,

or CAREA high

† This parameter is assured by simulation and is not tested.

NOTE 6: Under certain circumstances these outputs also can transition asynchronously. These transitions occur when controller timing register

values are modified by user programming. If the new register value forces the output to change states then this transition occurs without

regard to FCLK inputs.

FCLK0

FCLK1

HSYNCn, VSYNCn,

CSYNCn / HBLNKn

CBLNKn / VBLNKn

CAREAn

Figure 132. Video Interface Timing: FCLK Input and Video Outputs

TMS320C80GF Datasheet(PDF) 161 Page - Texas Instruments

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