TMS320C80GF datasheet(162/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

159

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

video interface timing: external sync inputs

When configured as inputs, the HSYNCn, VSYNCn, and CSYNCn signals may be driven asynchronously. The

following parameters apply only when the inputs are being generated synchronous to FCLKn in order to ensure

recognition on a particular FLCKn edge (see Figure 133).

NO.

MIN

MAX

UNIT

tsu(SIL-FCKH)

Setup time, HSYNC, VSYNC, or CSYNC low to FCLK no longer low†

th(FCKH-SIL)

Hold time, HSYNC, VSYNC, or CSYNC high after FCLK high‡

tsu(SIH-FCKH)

Setup time, HSYNC, VSYNC, or CSYNC high to FCLK no longer low§

th(FCKH-SIH)

Hold time, HSYNC, VSYNC, or CSYNC low after FCLK high¶

† This parameter must be met only to ensure the input is recognized as low at FLCK edge B.

‡ This parameter must be met only to ensure the input is recognized as high at FLCK edge A.

§ This parameter must be met only to ensure the input is recognized as high at FLCK edge D.

¶ This parameter must be met only to ensure the input is recognized as low at FLCK edge C.

FCLK0

FCLK1

HSYNC0, HSYNC1

VSYNC0, VSYNC1

CSYNC0, CSYNC1

(Inputs)

Figure 133. Video Interface Timing: External Sync Inputs

TMS320C80GF Datasheet(PDF) 162 Page - Texas Instruments