TMS320C80GF datasheet(164/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

161

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

emulator interface connection

The ’C80 supports emulation through a dedicated emulation port that is a superset of the IEEE Standard 1149.1

(JTAG) Standard. To support the ’C80 emulator, a target system must include a 14-pin header (2 rows of 7 pins)

with the connections shown in Figure 135.

TMS

TDI

PD(+3.3V)

TDO

TCKRET

TCK

EMU0

TRST

GND

No pin (key)

GND

EMU1

Pin Spacing: 0.100 in. (X,Y)

Pin Width: 0.025 in, square post

Pin Length: 0.235 in. nominal

(see Table 38)

Figure 135. Target System Header

Table 38. Target Connectors

XDS 510

SIGNAL

XDS 510

STATE

TARGET

STATE

DESCRIPTION

TMS

Test-mode select†

TDI

Test-data input†

TDO

Test-data output†

TCK

Test clock – 10 MHz clock source from emulator. Can be used to drive system-test clock.†

TRST

Test reset†

EMU0

I/O

Emulation pin 0

EMU1

I/O

Emulation pin 1

PD (3.3 V)

Presence detect. Indicates that the target is connected and powered up. Should be tied to

+ 3.3 V on target system.

TCKRET

Test clock return. Test clock input to the XDS 510 emulator. Can be buffered or unbuffered

version of TCK.†

† IEEE Standard 1149.1.

For best results, the emulation header should be located as close as possible to the ’C80. If the distance exceeds

six inches, the emulation signals should be buffered. See Figure 136.

TMS320C80GF Datasheet(PDF) 164 Page - Texas Instruments

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