TMS320C80GF datasheet(155/171 Pages) TI

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TMS320C80

DIGITAL SIGNAL PROCESSOR

SPRS023B – JULY 1994 – REVISED OCTOBER 1997

152

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

local bus timing: 2 cycle/column CAS timing

These timing parameters apply to the CAS/DQM[7:0] signals during 2 cycle per column memory accesses only.

They should be used in place of the general output and data input timing parameters when the 2 cycle/column

(non user-timed) cycle timing is selected (CT[2:0] inputs = 0b110). The value

n as used in the parameters

represents the integral number of half cycles between the transitions of the signals in question (see Figure 126).

NO.

’C80-40

’C80-50

’C80-60

UNIT

MIN

MAX

MIN

MAX

tw(CASH)

Pulse duration, CAS/DQM high

tH–2

tw(CASL)

Pulse duration, CAS/DQM low

3tH–11

3tH–9.5

th(OUTV-CASL)

Hold time, CAS/DQM high after output valid

D[63:0]

A[31:0], STATUS[5:0]

DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W

ntH–5

ntH–4.5

ntH–3.5

ntH–4.5

ntH–3.5

ntH–3

th(CASL-OUTV)

Hold time, output valid after CAS/DQM low

ntH–11

ntH–9.5

ta(CASL-DV)

Access time, data valid from CAS/DQM low

3tH–12

th(CASH-DV)

Hold time, data valid after CAS/DQM high

CLKOUT

Output

D[63:0]

CAS/DQM[7:0]

Figure 126. 2 Cycle / Column CAS Timing

TMS320C80GF Datasheet(PDF) 155 Page - Texas Instruments

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