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TMS320C80GF Datasheet(PDF) 154 Page - Texas Instruments |
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TMS320C80GF Datasheet(HTML) 154 Page - Texas Instruments |
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154 / 171 page ![]() TMS320C80 DIGITAL SIGNAL PROCESSOR SPRS023B – JULY 1994 – REVISED OCTOBER 1997 151 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 data input timing The following general timing parameters apply to the D[63:0] inputs unless otherwise specifically given. The value n as used in the parameters represents the integral number of half cycles between the transitions of the output and input in question (see Figure 125). NO PARAMETER ’C80-40 ’C80-50 ’C80-60 UNIT NO. PARAMETER MIN MAX MIN MAX MIN MAX UNIT 34 ta(CKOH-DV) Access time, CLKOUT high to D[63:0] valid ntH–8 ntH–5.3 ntH–4.0 ns 35 ta(CKOL-DV) Access time, CLKOUT low to D[63:0] valid ntH–8 ntH–6.5 ntH–6.5 ns 36 tsu(DV-CKOH) Setup time, D[63:0] valid to CLKOUT no longer low 8 6.1 6.1 ns 37 tsu(DV-CKOL) Setup time, D[63:0] valid to CLKOUT no longer high 8 6.1 6.1 ns 38 th(CKOL-DV) Hold time, D[63:0] valid after CLKOUT low 2 2 2 ns 39 th(CKOH-DV) Hold time, D[63:0] valid after CLKOUT high 2 2 2 ns 40 ta(OUTV-DV) Access time, output valid to D[63:0] inputs valid A[31:0], CAS/DQM[7:0]†, STATUS[5:0] DBEN, DDIN, DSF, RAS, RL, TRG/CAS, W ntH–9 ntH–8 ntH–7 ntH–6.5 ntH–7 ntH–6.5 ns 41 th(OUTV-DV)‡ Hold time, D[63:0] valid after output valid RAS, CAS/DQM[7:0] A[31:0] 2 3 2 3 2 3 ns † Except CAS/DQM[7:0] during non user-timed 2 cycle/column accesses ‡ Applies to RAS, CAS/DQM[7:0], and A[31:0] transitions that occur on CLKOUT edge coincident with input data sampling CLKOUT D[63:0] Output tH tH tH tH tH tH tH tH tH tH tH tH 34 38 36 35 39 37 40 41 Figure 125. Data-Input Timing |
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