TUSB6250 datasheet(52/124 Pages) TI

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8−11

SLLS535A − January 2004

TUSB6250

is already a WAKCLK interrupt in the queue. This avoids the MCU being interrupted by too many WAKCLK

interrupts.

•

Following the same guide line, when consecutive status change events happen:

•

If the source of the new status change event that occurred is different from the ones that already

occurred, the new status change event is logged in the corresponding status change bit of the

USBWKUP register. For example, if the CDCHG bit is already set, but VBUSCHG bit is not set, a new

VBUS status change causes the VBUSCHG bit to be set, although it might not trigger a new WAKCLK

interrupt if the current WAKCLK interrupt is still in the queue.

•

If the source of the new status change event occurred is the same as the ones that already occurred,

the new status change event is ignored. For example, if CDCHG bit is still set, but a new CDCHG event

is detected, the new CDCHG status change event is ignored. This avoids unnecessary changes in the

status change bits of the USBWKUP register caused by redundant status change events.

•

For detailed information regarding the WAKCLK interrupt, see section 8.3.20.

•

Even if the WAKCLK interrupt is not enabled, the status change events can still be observed by polling

the MCUCNFG register, as long as the event detection is enabled in the MCUCNFG register.

The CD1STEN and CD2STEN bits in the MCUCNFG register can be individually enabled for separate wakeup

event detection. However, since these two bits share the same status change indication bit (CDCHG) in the

USB wakeup reason register, clearing one interrupt source results in the interrupt source indication of the other

being cleared at the same time.

To avoid missing status changes on the port 3 GPIO, especially in the suspend condition in which the clock

may be shut down, the following two sets of circuitries are used for generating the four status change bits (bit

7 to 4).

•

De-bounced status change circuitry is used whenever the clock is available and stable. The de-bouncing

time interval is 1.28 ms, which means that only switching lasting longer than 1.28 ms is considered a valid

logic transition on the related port3 GPIO pin.

•

Asynchronously-triggered status change circuitry is used to latch the change event when the remote

wakeup is disabled and the low-power enable is true (LPEN bit in USBCTL is set), while the TUSB6250

is in the suspend state.

Bits [3:0] provide the de-bounced read-only value of the current logic level on the corresponding GPIO pins

of port3. The de-bouncing time interval is 1.28 ms.

The USBWKUP register is cleared by a power-up reset or a WDT reset. A USB reset can not clear the

USBWKUP register.

765

43210

P35CHG

P34CHG

VBUSCHG

CDCHG

P35ST

P34ST

CD2ST

CD1ST

R/C

R/O

BIT

NAME

RESET

FUNCTION

CD1ST

Compact flash card/media detection CD1 status bit. This bit represents the de-bounced status value

on the CD1 pin.

CD1ST = 1 CF card/media is not inserted.

CD1ST = 0 CF card/media may be inserted (a firm insertion depends on the status on both media

detection pins).

CD2ST

Compact flash card/media detection CD2 status bit. This bit represents the de-bounced status value

on the CD2 pin.

CD2ST = 1 CF card/media is not inserted.

CD2ST = 0 CF card/media may be inserted (a firm insertion depends on the status on both media

detection pins).

P34ST

P3.4 status bit. This bit represents the de-bounced status value on the P3.4 pin.

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