AD9213 datasheet(109/110 Pages) AD

109 / 110 page

Data Sheet

AD9213

Rev. A | Page 109 of 109



Write Register 0x1602 = 0x03. This is points to Clock

Rate 3 and contains coefficients for the user selected clock

frequency (Clock Rate 3).

The coefficients for 10 GSPS are initially stored in all four

locations by default.

The first time a sample clock frequency is used, a few seconds

are required for the coefficients to converge and store as Clock

Rate 0, Clock Rate 1, Clock Rate 2, or Clock Rate 3. In the next

instance a specific clock rate is used with its associated set of

stored coefficients, only a few microseconds are required to

make the change. Note that additional time is required for the

device to perform the SPI writes described in this section.

This procedure must be performed from the beginning if the

AD9213 is powered down.

POWER SUPPLY RECOMMENDATIONS

Several of the AD9213 supply domains can be combined and

desired. This is an example configuration for minimizing power

supply components and power domains. This approach can

slightly increase the risk of switching regulator artifacts being

injected into the power supply domains of the ADC. Initial

evaluations using this configuration suggest the noise impact is

minimal and is typically outweighed by its simplicity and use of

fewer power supply components. Use of linear regulators and

isolating specific supply pins can result in less noise.

An effective way to add power supply bypass capacitance to the

AD9213 PCB is to use through vias on the AD9213 BGA power

pads. Use 0201 (0603 Metric), 0.1 μF surface mount capacitors

directly below the BGA footprint on the opposite side of the

board, connecting the supply pins to the adjacent ground pins.

Surface mount solder pads are required to accommodate the

capacitors.

All ground pins can be connected to the same planes and

combined into one domain at the board level

12V

NOTES

1. BYPASS CAPACITORS NOT SHOWN.

VOUT1

1.5V

AVDD

FVDD

VDD_NVG

VOUT2

LTM4644-1

AD9213

VOUT3

VOUT4

BVDD2

RVDD2

PLLVDD2

TMU_AVDD2

BVNN1

AVNN1

BVNN2 INTERNALLY GENERATED

BVDD3

VNEG_OUT

SVDD2

JVDD2

DVDD

CLKVDD_LF

JVDD

JVTT

TMU_DVDD

AVDDFS8

2.5V

1V ANALOG

1V DIGITAL

2V DIGITAL

2V ANALOG

AVNN1, BVNN1

CONNECTED TO

VNEG_OUT

ADP1764

ADP7157

Figure 126. Alternate Simplified Power Supply Configuration

AD9213 Datasheet(PDF) 109 Page - Analog Devices

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