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DSA504RT Datasheet(PDF) 23 Page - Microchip Technology |
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DSA504RT Datasheet(HTML) 23 Page - Microchip Technology |
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23 / 73 page ![]() DSA504RT Register Map Preliminary Data Sheet © 2025 Microchip Technology Inc. and its subsidiaries DS50004033A - 23 4:0 sel_gpio1_func GPIO1 pin function select. See the sel_gpio0_func description at address 0x51. Address: Name: Default: Type: 0x0053 config_0x53 0x00 R/W Bit Field Function Name Description 7 fusa_en_lol FUSA FAULT0 PLL_LOL enable. 0 = disable 1 = enable 6:5 sel_bank_fs0 Register bit for FS0 frequency select. Ignored if any GPIO is configured for FS0 in its sel_gpioX_func register field. FS0 selects frequency plan A or B for the back-end dividers (i.e. the output dividers). 0 = disabled 1 = disabled 2 = frequency plan A (if FS1=0) or frequency plan B (if FS1=1) 3 = frequency plan for each output set by corresponding sel_bank_bed bit (if FS1=0) or !sel_bank_bed (if FS1=1) For decodes 0 and 1, FS0 is disabled and FS1 selects the frequency plan for the output dividers along with the rest of the device. In decode 3 above 'sel_bank_bed' means the frequency plan for each output divider is specified by its sel_bank_bed bit in register config_0x4F_50. 4:0 sel_gpio2_func GPIO2 pin function select. See the sel_gpio0_func description at address 0x51. Address: Name: Default: Type: 0x0054 config_0x54 0x00 R/W Bit Field Function Name Description 7 fusa_clr_ts FUSA FAULT2 Temperature Sensor clear trigger signal. 0 = normal operation 0->1 transition clears flag 6 fusa_en_los FUSA FAULT1 PLL_LOS enable. 0 = disable 1 = enable 5 fusa_clr_los FUSA FAULT1 PLL_LOS clear trigger signal. 0 = normal operation 0->1 transition clears flag 4:0 sel_gpio3_func GPIO3 pin function select. See the sel_gpio0_func description at address 0x51. Address: Name: Default: Type: 0x0055 config_0x55 0x00 R/W Bit Field Function Name Description |
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