DSA504RT datasheet(40/73 Pages) MICROCHIP

40 / 73 page

DSA504RT

Preliminary Data Sheet

DS50004033A - 40

Address:

Name:

Default:

Type:

0x0083

apll_config1

0xE8

R/W

Bit Field

Function Name

Description

7:6

js_order

APLL frequency plan A feedback divider sigma-delta modulation order.

0 = no sigma delta (fractional bits ignored)

1 = js1. no shaping (integer mode)

2 = js2. 20dB/decade — do not use

3 = js3. 40dB/decade (fractional mode)

5:3

pfd_ctl_432

APLL frequency plan A PFD anti-backlash width setting and PFD boost.

0 = 250ps

1 = 700ps

2 = 250ps (boost)

3 = 350ps (boost)

4 = 1000ps

5 = 1200ps

6 = 1400ps

7 = 1600ps

2:0

podivn

APLL output divider post-divider value.

0 = divide by 1

1 = divide by 2

2 = divide by 4

3 = divide by 6

other = divide by 8

Address:

Name:

Default:

Type:

0x0084:0x0085

afbden

0x0000

R/W

Bit Field

Function Name

Description

15:0

—

APLL fractional divider denominator. Can be used with afbrem to

sigma-delta modulate the APLL fractional divider lsb when 0ppm

frequency conversion from CLKIN is required.

Address:

Name:

Default:

Type:

0x0086:0x0087

afbrem

0x0000

R/W

Bit Field

Function Name

Description

15:0

—

APLL fractional divider remainder. Can be used with afbden to sigma-

delta modulate the APLL fractional divider lsb when 0ppm frequency

conversion from CLKIN is required.

DSA504RT Datasheet(PDF) 40 Page - Microchip Technology

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