DSA504RT datasheet(50/73 Pages) MICROCHIP

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DSA504RT

Preliminary Data Sheet

DS50004033A - 50

5:0

FDIV2 frequency plan A fraction bit position. This defines the lsb of the

fd2_div register's fractional bits below which the fd2_rem and fd2_den

can be used for sigma delta modulation for exact 0ppm frequency

conversion from the CLKIN signal. Number of bits used is 36-bp.

0 = 36 fractional bits(default)

…

12 = 24 fractional bits

Address:

Name:

Default:

Type:

0x00D4

fd2_config3

0x00

R/W

Bit Field

Function Name

Description

enss

FDIV2 frequency plan A spread spectrum enable.

0 = Disabled

1 = Enabled

dwnen

FDIV2 frequency plan A spread spectrum down vs. center spread.

0 = Center

1 = Down

fr_wide

FDIV2 frequency plan A phase interpolator for div=4 selector.

0 = Normal

1 = div=4

4:0

reserved

Used to store calibration information. Please do not overwrite.

Address:

Name:

Default:

Type:

0x00D5:0x00D9

fd2_div_b

0x0000000000

R/W

Bit Field

Function Name

Description

39:0

—

FDIV2 frequency plan B fractional divider value. Bits 39:36 are integer.

Bits 35:0 are fraction.

Address:

Name:

Default:

Type:

0x00DA:0x00DD

fd2_ss_id_b

0x00000000

R/W

Bit Field

Function Name

Description

31:0

—

FDIV2 frequency plan B spread spectrum increment/decrement value.

Address:

Name:

Default:

Type:

0x00DE:0x00DF

fd2_ss_cnt_b

0x0000

R/W

Bit Field

Function Name

Description

15:0

—

FDIV2 frequency plan B spread spectrum count value.

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