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DSA504RT Datasheet(PDF) 56 Page - Microchip Technology

Part # DSA504RT
Description  Low-Power, Low-Jitter, Six-Output Clock Generator for Space Applications
PDF  73 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

DSA504RT Datasheet(HTML) 56 Page - Microchip Technology

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DSA504RT
Electrical Characteristics
 Preliminary Data Sheet
© 2025 Microchip Technology Inc. and its subsidiaries
DS50004033A - 56
Table 6-8. AC Electrical Characteristics (continued)
Electrical Characteristics: Unless otherwise indicated, VDD = 3.3V ±10%, VDD = 2.5V ±10%, VDD = 1.8V +10%/-5%, CLOAD =
2pF, TA = –40°C to +105°C.
Parameter
Symbol
Min.
Typ.
Max.
Units Condition
Input-to-Output
Delay
tPD
—
TBD
—
ns
PLL-Bypass mode
Output Enable Time
tEN
—
TBD
—
cycles Output frequency cycle
Output Disable
Time
tDIS
—
TBD
—
cycles Output frequency cycle
Frequency Stability
ΔfS
—
—
TBD
ppm —
Aging
ΔfA
—
—
±5
ppm 1st year @ 25⁰C
—
—
±1
ppm Per year after 1st year
RMS Jitter
Generation, PLL
Locked to External
Crystal Oscillator.
JGENMO
—
130
—
fs
INT Mode, 12kHz to 20 MHz @ 100 MHz,
Note 7
—
150
—
fs
FRAC Mode, 12 kHz to 20 MHz @ 100
MHz, Note 7
RMS Jitter as per
PCIe 5.0 (PLL_BW =
0.5 to 1.8MHz, CDR
for 32 GT/s CC)
tjPCIe_5.0
—
12
—
fs
SSC off
—
25
—
SSC – 0.3%
—
25
—
SSC – 0.5%
RMS Jitter as per
PCIe 6.0 (PLL_BW =
0.5 to 1MHz, CDR
for 64 GT/s CC)
tjPCIe_6.0
—
9
—
fs
SSC off
—
18
—
SSC – 0.3%
—
18
—
SSC – 0.5%
RMS Jitter as per
PCIe 7.0 (PLL_BW =
0.35 to 1.8MHz, CDR
for 128 GT/s CC)
tjPCIe_7.0
—
6
—
fs
SSC off
—
13
—
SSC – 0.3%
—
13
—
SSC – 0.5%
Spread Spectrum
Modulation
Frequency
fSSC
30
—
33
kHz
—
Spread Spectrum
Frequency Deviation
fSSCdev
–2.5
—
2.5
%
Center Spread
–2.5
—
0
%
Down Spread
1. Measurement taken from a single-ended waveform.
2. Defined as the maximum instantaneous voltage including overshoot.
3. Defined as the minimum instantaneous voltage including undershoot.
4. Noise spur amplitude measured with 100mVPP sine wave added to 3.3V VCCO for 156.25MHz carrier frequency.
5. Measured across two adjacent LVDS outputs with the victim running at 155.52MHz and the aggressor running at
156.25MHz, other outputs being disabled.
6. Measurement taken from differential waveform.
7. All jitter measurements are done with one output enabled @ 100MHz and set to LPHCSL differential format.
6.4.1.
LVPECL AC Electrical Characteristics
The following table lists the LVPECL AC electrical characteristics details.



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