DSA504RT datasheet(28/73 Pages) MICROCHIP

28 / 73 page

DSA504RT

Preliminary Data Sheet

DS50004033A - 28

Address:

Name:

Default:

Type:

0x005B

config_0x5B

0x20

R/W

Bit Field

Function Name

Description

afb_en_rem_den

APLL frequency plan A remainder and denominator selector.

0 = Disabled, internal rem=0, den=1

1 = Enable, use registers afbrem and afbden

6:5

rfdivn

Frequency plan A reference clock doubler/divider selector.

0 = 1x (pass refclk)

1 = 2x (refclk*2)

2 = 0.5x (refclk/2)

3 = 0.25x (refclk/4)

4:0

tc_ndiv

Frequency plan A system clock divider between 2 to 16.

tc_ndiv=fbclk_MHz/16 (openloop=4).

Address:

Name:

Default:

Type:

0x005C

config_0x5C

0xAA

R/W

Bit Field

Function Name

Description

ref_clk_mwidth

Frequency plan A REF clock minimum width selector when rfdivn is

doubling.

0 = disable (minimum width)

1 = enable (minimum width when APLL REF > 90MHz and rfdivn=1)

6:5

rfdivn_b

Frequency plan B reference clock doubler/divider selector.

0 = 1x (pass refclk)

1 = 2x (refclk*2)

2 = 0.5x (refclk/2)

3 = 0.25x (refclk/4)

4:0

tc_ndiv_b

Frequency plan B system clock divider between 2 to 16.

tc_ndiv=fbclk_MHz/16 (openloop=4).

DSA504RT Datasheet(PDF) 28 Page - Microchip Technology

DSA504RT Datasheet(HTML) 28 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

Datasheet Download

Link URL