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DSA504RT Datasheet(PDF) 32 Page - Microchip Technology |
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DSA504RT Datasheet(HTML) 32 Page - Microchip Technology |
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32 / 73 page ![]() DSA504RT Register Map Preliminary Data Sheet © 2025 Microchip Technology Inc. and its subsidiaries DS50004033A - 32 5 cmos_drvp OUT0 CMOS drive strength 0 = 1x (drive strength 0) 1 = 2x (drive strength 1) See Table 5-7 and its notes for VOH, VOL, IOH, and IOL values. 4 cmos_drvn OUT0b CMOS drive strength 0 = 1x (drive strength 0) 1 = 2x (drive strength 1) See Table 5-7 and its notes for VOH, VOL, IOH, and IOL values. 3 cmos_edge_n[2] Concatenated with cmos_edge_n[1:0] in the output0_config1 register at 0x5F:0x60. 2:0 cmos_edge_p OUT0 CMOS edge p control 000 = minimum edge rate 001 = second smallest edge rate … 111 = maximum edge rate Address: Name: Default: Type: 0x0062 output0_config3 0x00 R/W Bit Field Function Name Description 7:5 reserved — 4 pecl_lvds_res Output buffer LVPECL and LVDS signal swing control 0 = Normal 1 = 100mV smaller 3 hcsl_en42ohm Output buffer LPHCSL output impedance selector 0 = 50Ω 1 = 42Ω 2 ldo_en OUT0 buffer enable LDO selector 0 = Disable 1 = Enable 1 en_mod18 OUT0 LVCMOS bias selector for duty cycle enhancement at 1.8V 0 = Normal duty cycle 1 = Enhancement for 1.8V 0 cmos_p_disable OUT0 disable 0 = Enabled 1 = Disabled (high-impedance) Address: Name: Default: Type: 0x0063:0x0064 output1_config0 0x0200 R/W Bit Field Function Name Description 15 reserved — 14:11 mode OUT1 output buffer mode selector. See output0_config0::mode at 0x5D:0x5E. 10:0 bdiv_val_b OUT1 buffer divider ratio, frequency plan B. See output0_config0::bdiv_val_b at 0x5D:0x5E. |
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