DSA504RT datasheet(8/73 Pages) MICROCHIP

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DSA504RT

Functional Description

Preliminary Data Sheet

DS50004033A - 8

Functional Description

DSA504RT is high performance, low jitter, six-output programmable clock generators that make

each device a good oscillator-clock-generator-fanout-buffer combination replacement in many

applications.

The internal high-performance PLL locks to an external reference clock signal. While using the

external reference clock, this device can simultaneously be used as a fanout buffer for the external

reference clock. Thus, it offers clock generator and clock buffer function combinations. In the buffer

configuration, the external clock is routed directly from the input to the crossbar at the output.

DSA504RT can accept an external differential clock up to 250 MHz and a single-ended LVCMOS up

to 200 MHz. It combines excellent jitter and stability performance with very low power consumption

over a wide range of supply voltages and temperatures.

With its high performance PLL and wide range VCO, followed by two integer dividers, two fractional

dividers, and a crossbar, each device can synthesize frequencies up to 662 MHz (LVPECL and

LVDS outputs), up to 250 MHz (LPHCSL output), up to 200 MHz (LVCMOS output), and provide

any frequency in the specified range on any output. Furthermore, each output buffer integrates a

back-end integer divider for more frequency flexibility. Each output buffer has a dedicated power

pin with an internal LDO to provide separate output level selection and minimize crosstalk between

outputs.

DSA504RT includes functional safety features required by some applications and have spread

spectrum capability for better EMI control. They also feature GPIO pins and an I2C serial interface.

Each GPIO pin can be configured to perform a specific function according to Table 3-1. The I2C

interface can be used to read back or modify user registers, reboot the part to reset it to its factory

settings, and clear any functional safety flags.

Custom configurations can be created using Microchip’s Timing GUI software available on the

corresponding products’ web pages.

Microchip can program the device OTP memory with the required configuration and provide the

user with custom-programmed parts (see the Product Identification System section). Such custom-

programmed parts will come up with the required settings on every power-up. Additionally, the

device’s OTP memory can be programmed using the OTP programmer tools provided in the

DSA504RT evaluation kits.

3.1.

Startup

Once core VDD (Pins 3, 8, and 28) supply voltages are applied, the device starts the initialization

phase which ends by uploading the content of the OTP non-volatile memory into shadow registers.

The chip will typically start 3ms after the power supply is applied. For minimal start delay, apply core

VDD and VDDOx at the same time. If VDDOx are applied before the core VDD, the outputs are kept

disabled until a stable clock is available at the crossbar output. The off state of the outputs can be

selected to be Hi-Z or Low-High. VDDOx should not be delayed for more than 1.5ms than the core

VDD to ensure the buffers are synchronized.

3.2.

Input Reference Selection

The PLL reference clock of DSA504RT always uses an external clock source. This configuration is set

by default in OTP during the factory programming. The sel_refclk field is set in the configuration

3.3.

Input Reference Interface

By default, clock inputs (CLKIN/CLKINb) accept differential HCSL signals and can be programmed to

accept single-ended LVCMOS at CLKIN (Pin 1) while CLKINb (Pin 2) becomes a GPI (General Purpose

Input). The diagrams in Figure 3-1 through Figure 3-5 show how to interface the device input to

LPHCSL, HCSL, LVCMOS, LVDS and LVPECL outputs respectively.

DSA504RT Datasheet(PDF) 8 Page - Microchip Technology

DSA504RT Datasheet(HTML) 8 Page - Microchip Technology

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