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DSA504RT Datasheet(PDF) 7 Page - Microchip Technology

Part # DSA504RT
Description  Low-Power, Low-Jitter, Six-Output Clock Generator for Space Applications
PDF  73 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

DSA504RT Datasheet(HTML) 7 Page - Microchip Technology

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DSA504RT
Pin Description
 Preliminary Data Sheet
© 2025 Microchip Technology Inc. and its subsidiaries
DS50004033A - 7
Table 2-1. DSA504RT Pin Description (continued)
Pin Number for
VQFN Package
Pin Number for
CQFP Package
Pin Names
Description
11
12
VDDO0
VDD for OUT0/OUT0b
12
13
OUT1b
Complementary Output 1. Output logic can be selected to be
differential (LPHCSL, LVDS and LVPECL) or single-ended LVCMOS.
13
14
OUT1
True Output 1. Output logic can be selected to be differential
(LPHCSL, LVDS and LVPECL) or single-ended LVCMOS.
14
15
VDDO1
VDD for OUT1/OUT1b
—
16
GND
Ground
15
17
OUT2b
Complementary Output 2. Output logic can be selected to be
differential (LHCSL, LVDS and LVPECL) or single-ended LVCMOS.
16
18
OUT2
True Output 1. Output logic can be selected to be differential
(LPHCSL, LVDS and LVPECL) or single-ended LVCMOS.
17
19
VDDO2
VDD for OUT2/OUT2b
18
20
GND
Ground
19
21
OUT3b
Complementary Output 3. Output logic can be selected to be
differential (LPHCSL, LVDS and LVPECL) or single-ended LVCMOS.
20
22
OUT3
True Output 3. Output logic can be selected to be differential
(LPHCSL, LVDS and LVPECL) or single-ended LVCMOS.
21
23
VDDO3
VDD for OUT3/OUT3b
—
24
GND
Ground
22
25
OUT4b
Complementary Output 4. Output logic can be selected to be
differential (LPHCSL, LVDS and LVPECL) or single-ended LVCMOS.
23
26
OUT4
True Output 4. Output logic can be selected to be differential
(LPHCSL, LVDS and LVPECL) or single-ended LVCMOS.
24
27
VDDO4
VDD for OUT4/OUT4b
25
28
OUT5b
Complementary Output 5. Output logic can be selected to be
differential (LPHCSL, LVDS and LVPECL) or single-ended LVCMOS.
26
29
OUT5
True Output 5. Output logic can be selected to be differential
(LPHCSL, LVDS and LVPECL) or single-ended LVCMOS.
27
30
VDDO5
VDD for OUT5/OUT5b
28
31
VDD
VDD for the core.
VDD pins 3, 8, and 28 should be connected to the same power
supply.
—
32
GND
Ground
29
—
EPAD/Tie-bar
Ground



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