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DSA504RT Datasheet(PDF) 45 Page - Microchip Technology |
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DSA504RT Datasheet(HTML) 45 Page - Microchip Technology |
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45 / 73 page ![]() DSA504RT Register Map Preliminary Data Sheet © 2025 Microchip Technology Inc. and its subsidiaries DS50004033A - 45 Address: Name: Default: Type: 0x00A8:0x00A9 fd1_rem 0x0000 R/W Bit Field Function Name Description 15:0 — FDIV1 fractional divider denominator. Can be used with fd1_den to sigma-delta modulate FDIV1's lsb when 0ppm frequency conversion from CLKIN is required. Address: Name: Default: Type: 0x00AA:0x00AB fd1_ss_cnt 0x0000 R/W Bit Field Function Name Description 15:0 — FDIV1 frequency plan A spread spectrum count value. Address: Name: Default: Type: 0x00AC:0x00AF fd1_ss_id 0x00000000 R/W Bit Field Function Name Description 31:0 — FDIV1 frequency plan A spread spectrum count value. Address: Name: Default: Type: 0x00B0 fd1_config0 0x30 R/W Bit Field Function Name Description 7:6 fr_pdivn FDIV1 frequency plan A. fractional divider post-divider. 0 = div 1 (bypass; not recommended), 1 = div 2 (typical value) 2 = div 4 3 = div 8 5:4 fr_pd FDIV1 frequency plan A fractional divider power down control. 0 = Enable 3 = Power-down 3:0 reserved Address: Name: Default: Type: 0x00B1 fd1_config1 0x80 R/W Bit Field Function Name Description 7 mode FDIV1 div bits write mode. When writing fd1_div or fd1_div_b: 0 = Each byte latched separately when written (not recommended) 1 = All bytes of the multi-byte field are latched when the last byte (highest address) is written 6:0 fr_gain_doff_s FDIV1 frequency plan A gain offset. Signed 7-bit integer. |
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