DSA504RT datasheet(11/73 Pages) MICROCHIP

11 / 73 page

DSA504RT

Functional Description

Preliminary Data Sheet

DS50004033A - 11

Figure 3-6. OEx Assertion (Output Enable) Timing Diagram

Figure 3-7. OEx Deassertion (Output Disable) Timing Diagram

3.5.

Outputs Type Control

Each of the six output buffers is powered through a dedicated pin and an internal LDO. Separate

output buffers’ voltage supplies provide less crosstalk between outputs and, therefore, offer

better jitter performance and more flexibility in interfacing the outputs. The output format is set

independently for each output to be differential (LVPECL, LVDS, or LPHCSL) or single-ended LVCMOS

to offer up to six differential outputs or up to 12 LVCMOS outputs.

3.6.

Output LVCMOS Polarity

When LVCMOS format is selected, each pair of CMOS signals generated from the same output

buffer can be programmed to be in phase or be complementary. The polarity of each of the two

outputs can be independently modified through the I2C serial interface, and each of the outputs can

be independently turned off to save power in case that particular one is not used.

3.7.

Output Frequency Selection

The desired output frequencies must be entered in the GUI software during part creation and

then the algorithm calculates the appropriate parameters (PLL feedback ratio, VCO frequency, and

dividers ratios). The output frequencies can also be selected from pre-stored frequency plan A,

frequency plan B, or from both (combination).

DSA504RT Datasheet(PDF) 11 Page - Microchip Technology