DSA504RT datasheet(26/73 Pages) MICROCHIP

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DSA504RT

Preliminary Data Sheet

DS50004033A - 26

3:0

chp_iprop_iint_b

APLL frequency plan B charge pump iprop (proportional current) / iint

(integral current).

0 = 100µA/25µA

1 = 200µA/25µA

2 = 300µA/25µA

3 = 400µA/25µA

4 = 500µA/50µA

5 = 600µA/50µA

6 = 700µA/50µA

7 = 800µA/50µA

8 = 1000µA/50µA

9 = 1000µA/100µA

10 = 1200µA/50µA

11 = 1200µA/100µA

12 = 1400µA/50µA

13 = 1400µA/100µA

14 = 1600µA/50µA

15 = 1600µA/100µA

Address:

Name:

Default:

Type:

0x0059

config_0x59

0x5D

R/W

Bit Field

Function Name

Description

reserved

ref_clk_mwidth_b

Frequency plan B REF clock minimum width selector when rfdivn is

doubling.

0 = disable (minimum width)

1 = enable (minimum width when APLL REF > 90MHz and rfdivn_b=1)

afb_en_rem_den_b

APLL frequency plan B remainder and denominator selector

0 = Disabled, internal rem=0, den=1

1 = Enable, use registers afbrem and afbden

4:3

js_order_b

APLL frequency plan B feedback divider sigma-delta modulation order.

0 = no sigma delta (fractional bits ignored)

1 = js1. no shaping (integer mode)

2 = js2. 20dB/decade — do not use

3 = js3. 40dB/decade (fractional mode)

2:0

pfd_ctl_432_b

Frequency plan B APLL PFD. Anti-backlash width setting and PFD boost.

0=250ps, mode 1x plateau width=0ps,

1=700ps, mode 1x plateau width=0ps,

2=250ps (boost mode 2x) plateau width=±80ps,

3=350ps (boost mode 2x) plateau width=±80ps,

4=1000ps, mode 1x plateau width=0ps,

5=1200ps, mode 1x plateau width=0ps,

6=1400ps, mode 1x plateau width=0ps,

7=1600ps, mode 1x plateau width=0ps

DSA504RT Datasheet(PDF) 26 Page - Microchip Technology

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