DSA504RT datasheet(36/73 Pages) MICROCHIP

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DSA504RT

Preliminary Data Sheet

DS50004033A - 36

Address:

Name:

Default:

Type:

0x0074

output3_config3

0x00

R/W

Bit Field

Function Name

Description

7:5

reserved

—

pecl_lvds_res

Output buffer LVPECL and LVDS signal swing control. See

output0_config3::pecl_lvds_res at 0x62.

hcsl_en42ohm

Output buffer LPHCSL output impedance selector. See

output0_config3::hcsl_en42ohm at 0x62.

ldo_en

OUT0 buffer enable LDO selector. See output0_config3::ldo_en at 0x62.

en_mod18

OUT0 LVCMOS bias selector for duty cycle enhancement at 1.8V. See

output0_config3::en_mod18 at 0x62.

cmos_p_disable

OUT0 disable. See output0_config3::cmos_p_disable at 0x62.

Address:

Name:

Default:

Type:

0x0075:0x0076

output4_config0

0x0200

R/W

Bit Field

Function Name

Description

reserved

—

14:11

mode

OUT4 output buffer mode selector. See output0_config0::mode at

0x5D:0x5E.

10:0

bdiv_val_b

OUT4 buffer divider ratio, frequency plan B. See

output0_config0::bdiv_val_b at 0x5D:0x5E.

Address:

Name:

Default:

Type:

0x0077:0x0078

output4_config1

0xDA00

R/W

Bit Field

Function Name

Description

15:14

cmos_edge_n

OUT4b CMOS edge rate selector. See output0_config1::cmos_edge_n at

0x5F:0x60.

cmos_n_disable

OUT4b disable. See output0_config1::cmos_n_disable at 0x5F:0x60.

12:11

en_pass_res

OUT4 reference voltage bias adjustment for ldo_variable (PECL, LVDS,

HCSL). See output0_config1::en_pass_res at 0x5F:0x60.

10:0

bdiv_val

OUT4 buffer divider ratio, frequency plan A. See

output0_config1::bdiv_val at 0x5F:0x60.

Address:

Name:

Default:

Type:

0x0079

output4_config2

0x03

R/W

Bit Field

Function Name

Description

OUT4 driver enable. See output0_config2::en at 0x61.

0 = Disabled

1 = Enabled

reserved

—

DSA504RT Datasheet(PDF) 36 Page - Microchip Technology

DSA504RT Datasheet(HTML) 36 Page - Microchip Technology

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