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DSA504RT Datasheet(PDF) 17 Page - Microchip Technology

Part # DSA504RT
Description  Low-Power, Low-Jitter, Six-Output Clock Generator for Space Applications
PDF  73 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

DSA504RT Datasheet(HTML) 17 Page - Microchip Technology

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DSA504RT
Host Interface
 Preliminary Data Sheet
© 2025 Microchip Technology Inc. and its subsidiaries
DS50004033A - 17
Table 4-3. I2C 10-bit CHIPID First 4 Byte Call Structure
Byte
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
1
1
1
1
1
0
CHIPID[9]
CHIPID[8]
0 or 1
2
CHIPID[7]
CHIPID[6]
CHIPID[5]
CHIPID[4]
CHIPID[3]
CHIPID[2]
CHIPID[1]
CHIPID[0]
3
ADDR[9]
ADDR[8]
ADDR[7]
ADDR[6]
ADDR[5]
ADDR[4]
ADDR[3]
ADDR[2]
4
ADDR[1]
ADDR[0]
0
0
0
0
0
0
4.3.
I2C Read Write Protocol
This section describes 7-bit and 10-bit operation protocols. The legend is shown below:
• S = Start Condition
• P = Stop Condition
• Sr = Repeated Start Condition
• 0 = Write Condition
• 1 = Read Condition
• A = Acknowledge
• N = Not Acknowledge
7-bit I2C Single Read
S Clt Addr [6:0]
0 A
Reg Addr #1
A
Reg Addr #2
A Sr Clt Addr [6:0] 1 A
Data
N P
7-bit I2C Burst Read
S
Clt Addr
[6:0]
0 A
Reg Addr
#1
A
Reg Addr
#2
A Sr
Clt Addr
[6:0]
1 A
Data
A
Data
N P
7-bit I2C Single Write
S
Clt Addr [6:0]
0
A
Reg Addr #1
A
Reg Addr #2
A
Data
A
P
7-bit I2C Burst Write
S
Clt Addr [6:0]
0
A
Reg Addr #1
A
Reg Addr #2
A
Data
A
Data
A
P
10-bit I2C Single Read
S Clt Addr #1
[9:0]
0 A Clt Addr #2
[9:0]
A
Reg Addr
#1
A
Reg Addr
#2
A Sr Clt Addr #1
[9:0]
1 A
Data
A P
10-bit I2C Burst Read
S Clt Addr
#1 [9:0]
0 A Clt Addr
#2 [9:0]
A Reg Addr
#1
A Reg Addr
#2
A Sr Clt Addr
#1 [9:0]
1 A
Data
A
Data
A P
10-bit I2C Single Write
S
Clt Addr #1
[9:0]
0
A
Clt Addr #2
[9:0]
A
Reg Addr #1
A
Reg Addr #2
A
Data
A
P
10-bit I2C Burst Write
S
Clt Addr #1
[9:0]
0 A
Clt Addr #2
[9:0]
A Reg Addr #1 A Reg Addr #2 A
Data
A
Data
A P



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