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DSA504RT Datasheet(PDF) 55 Page - Microchip Technology |
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DSA504RT Datasheet(HTML) 55 Page - Microchip Technology |
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55 / 73 page ![]() DSA504RT Electrical Characteristics Preliminary Data Sheet © 2025 Microchip Technology Inc. and its subsidiaries DS50004033A - 55 Table 6-7. LVCMOS DC Electrical Characteristics (continued) Electrical Characteristics: Unless otherwise indicated, VDD = 3.3V ±10%, VDD = 2.5V ±10%, VDD = 1.8V +10%/-5%, TA = –40°C to +105°C Parameter Symbol Min. Typ. Max. Units Condition Notes: 1. VOH measured at IOH = –6 mA/–3.5 mA/–2 mA for drive strength 0 and IOH = –10 mA/–6.5 mA/–4 mA for drive strength 1 when VDDO = 3.3V/2.5V/1.8V respectively. 2. VOL measured at IOL = 6 mA/3.5 mA/2 mA for drive strength 0 and IOL = 10 mA/6.5 mA/4 mA for drive strength 1 when VDDO = 3.3V/2.5V/1.8V respectively. 6.4. AC Electrical Characteristics The following table lists the AC electrical characteristics details. Table 6-8. AC Electrical Characteristics Electrical Characteristics: Unless otherwise indicated, VDD = 3.3V ±10%, VDD = 2.5V ±10%, VDD = 1.8V +10%/-5%, CLOAD = 2pF, TA = –40°C to +105°C. Parameter Symbol Min. Typ. Max. Units Condition Input Slew Rate SRIN 0.6 — — V/ns — Input Voltage Swing VASWING 0.15 — — Vdiff — Differential Absolute Max Input Voltage VIN(MAX) — — +1.15 V Note 1, Note 2 SE CMOS Absolute Max Input Voltage — — VDD + 0.3 V Note 1, Note 2 Differential Absolute Min Input Voltage VIN(MIN) –0.3 — — V Note 1, Note 3 SE CMOS Absolute Min Input Voltage –0.3 — — V Note 1, Note 3 Differential Input Frequency fIN 10 — 250 MHz PLL mode (no lower limit in buffer mode) Input Frequency (Single-Ended CMOS CLKIN) fIN_SE 10 — 200 MHz PLL mode (no lower limit for buffer mode) Input Duty Cycle IDC 35 — 65 % — Input Capacitance CIN — — 5 pF — Power Supply Rejection Ratio PSRRHSCL — TBD — dBc 10kHz sinusoidal noise, Note 4 — TBD — 100kHz sinusoidal noise, Note 4 — TBD — 500kHz sinusoidal noise, Note 4 — TBD — 1MHz sinusoidal noise, Note 4 Output-Output Crosstalk XTALK — TBD — dBc Note 5 Output Duty Cycle ODC 45 50 55 % Note 6, Figure 6-2, 50% input duty cycle, PLL mode Output-to-Output Skew tSKEW — 100 ps — Start-Up Time tSTART — 3 — ms — |
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