DSA504RT datasheet(46/73 Pages) MICROCHIP

46 / 73 page

DSA504RT

Preliminary Data Sheet

DS50004033A - 46

Address:

Name:

Default:

Type:

0x00B2

fd1_config2

0x00

R/W

Bit Field

Function Name

Description

fr_intg_mode

FDIV1 frequency plan A integer vs. fractional. Set this bit to match the

desired divide value for FDIV1.

0 = Fractional mode

1 = Integer mode

en_rem_den

FDIV1 frequency plan A remainder denominator enable.

0 = Disabled, use internal rem=0, den=1

1 = Enabled, use registers fd1_rem and fd1_den

5:0

FDIV1 frequency plan A fraction bit position. This defines the lsb of the

fd1_div register's fractional bits below which the fd1_rem and fd1_den

can be used for sigma delta modulation for exact 0ppm frequency

conversion from the CLKIN signal. Number of bits used is 36-bp.

0 = 36 fractional bits(default)

…

12 = 24 fractional bits

Address:

Name:

Default:

Type:

0x00B3

fd1_config3

0x00

R/W

Bit Field

Function Name

Description

enss

FDIV1 frequency plan A spread spectrum enable.

0 = Disabled

1 = Enabled

dwnen

FDIV1 frequency plan A spread spectrum down vs. center spread.

0 = Center

1 = Down

fr_wide

FDIV1 frequency plan A phase interpolator for div=4 selector.

0 = Normal

1 = div=4

4:0

reserved

Used to store calibration information. Please do not overwrite.

Address:

Name:

Default:

Type:

0x00B4:0x00B8

fd1_div_b

0x0000000000

R/W

Bit Field

Function Name

Description

39:0

—

FDIV1 frequency plan B fractional divider value. Bits 39:36 are integer.

Bits 35:0 are fraction.

DSA504RT Datasheet(PDF) 46 Page - Microchip Technology

DSA504RT Datasheet(HTML) 46 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73

Datasheet Download

Link URL