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DSA504RT Datasheet(PDF) 6 Page - Microchip Technology |
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DSA504RT Datasheet(HTML) 6 Page - Microchip Technology |
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6 / 73 page ![]() DSA504RT Pin Description Preliminary Data Sheet © 2025 Microchip Technology Inc. and its subsidiaries DS50004033A - 6 2. Pin Description The following figure shows the pin diagram and the table lists the pin names and its functional description. Figure 2-1. Pin Diagram Table 2-1. DSA504RT Pin Description Pin Number for VQFN Package Pin Number for CQFP Package Pin Names Description 1 1 CLKIN Differential Clock input/Single-Ended LVCMOS Clock Input. 2 2 CLKINb/GPI Differential Clock input/General Purpose input. If not used, pull down to GND. General Purpose Input/Output. This pin has a programmable internal (~100 kΩ) pull-down. 3 3 VDD VDD pins 3, 8, and 28 should be connected to the same power supply. 4 4 GND Ground 5 5 GPIO2 General Purpose Input/Output. This pin has an programmable internal (~100 kΩ) pull-up. 6 6 SDA I2C Data. This pin has a programmable internal (~100 kΩ) pull-up. 7 7 SCL I2C Clock. This pin has a programmable internal (~100 kΩ) pull-up. — 8 GND Ground 8 9 VDD VDD for the digital block. VDD pins 3, 8, and 28 should be connected to the same power supply. 9 10 OUT0b Complementary Output 0. Output logic can be selected to be differential (LPHCSL, LVDS and LVPECL) or single-ended LVCMOS. 10 11 OUT0 True Output 0. Output logic can be selected to be differential (LPHCSL, LVDS and LVPECL) or single-ended LVCMOS. |
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