EM77950 datasheet(34/102 Pages) EMC

34 / 102 page

EM77950

BB Controller

•

Product Specification (V1.0) 10.09.2007

(This specification is subject to change without further notice)

All the bits of PC are set "0"s as a reset condition occurs.

"RET" ("RETL k", "RETI") instruction loads the program counter with the contents

at the top of stack.

"MOV R2, A" allows the loading of an address from the "A" register to the lower 8

bits of the PC, and the high byte (A8~A14) of the PC remain unchanged.

"ADD R2, A" & "TBL" allows a corresponding address / offset be added to the

current PC.

7.1.4 Status Register – SR (0x03)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RST

Bit 0 (C):

Carry flag. This bit indicates that a carry out of ALU occurred during the last

arithmetic operation. This bit is also affected during bit test, branch

instruction and bit shifts.

Bit 1 (DC):

Auxiliary carry flag. This bit is set during ADD and ADC operations to

indicate that a carry occurred between Bit 3 and Bit 4.

Bit 2 (Z):

Zero flag. Set to "1" if the result of the last arithmetic, data or logic operation

is zero.

Bit 3 (P):

Power down bit. Set to 1 during power on or by a "WDTC" command and

reset to 0 by a "SLEP" command.

Bit 4 (T):

Time-out bit. Set to 1 by the "SLEP" command and the "WDTC" command, or

during power up and reset to 0 by WDT timeout.

Bit 5 (RST):

Set if the CPU wakes up by keying Wake-up pins. Reset if the chip wakes

up from other ways.

Bits 6 and 7

are reserved.

7.1.5 RAM Bank Selector – RAMBS0 (0x04), and RAMBS1 (0x07)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RAMBSX2 RAMBSX1 RAMBSX0

As depicted in Fig. 6-2, there are seven available banks in the MCU. Each of them

have 128 registers and can be accessed by defining the bits, RAMBSX0 ~ RAMBSX2,

as shown below.

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