EM77950 datasheet(56/102 Pages) EMC

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EM77950

BB Controller

•

Product Specification (V1.0) 10.09.2007

(This specification is subject to change without further notice)

There are 8 events in the BB that can cause the INT pin to go from low to high:

LOCK_IN – This interrupt indicates that the BB has started receiving a new

packet. The Preamble has been identified. If the NET_ID or/and the NODE_ID

are enabled, then they have been identified correctly. This event signals the

beginning of an incoming packet.

LOCK OUT – BB has just finished receiving a packet. This means that if the BB is

in fixed packet size mode, then it has finished receiving PSR bytes not including

CRC bytes. If BB is not in fixed packet size mode, then it has just finished

receiving a packet of size as indicated in the packet header. Although RX_STOP

and setting TX_RX=1 (SCR2) terminate the receiving of the packet, they do not

cause a LOCK_OUT event, since the MCU is already aware of it (the MCU

initiated it). The LOCK_OUT interrupt tells the MCU when to get data out of the

RX_FIFO.

LINK_DIS – This interrupt indicates that a “Zero counter” capacitor discharge

event has occurred. If a consecutive number of zero bits (according to SCR3

(4:6)) have been received, this interrupt is set, even if zero count capacitor

discharge is disabled (SCR3 (3) – EN_ZERO_DIS = ’0’). The actual capacitor

discharge and its interrupt are two separate registers (IER (2) for the interrupt and

SCR3 (3) for the discharge).

RX_OF – This interrupt indicates that a byte from an incoming packet was

discarded, since the RX_FIFO was already full. The receiver module tried to write

a byte to a full RX_FIFO. The MCU should know that the corresponding packet is

corrupted, since it is lacking at least one byte.

TX_EMPTY – The BB has finished transmitting a packet. Meaning, the transmit

shift register is empty and BB is now in RX mode (not TX mode).

RX_FIFO_AF – RX_FIFO is almost full. If the MCU does not want the RX_FIFO

to overflow, then it should empty it.

TX_FIFO_AE – TX_FIFO is almost empty. If the MCU did not finish putting the

transmitted packet in the TX_FIFO, then it should continue doing so now.

CS – CS status line has gone from “1” to “0” invokes a CS interrupt. This signals

the MCU that an unidentified (NET_ID or NODE_ID or Preamble were not

identified) packet has ended. If the MCU has a packet to transmit, and CS=”1”

than the MCU waits for this event.

All these events can be masked. If an event is masked, then even if that event occurs

- it does not set the INT pin to “1”. The masking is done by register IER.

The reason for masking is that in different applications or in different situation in the

same application these events have different priorities. The MCU determines which of

these events will invoke an MCU interrupt.

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