EM77950 datasheet(69/102 Pages) EMC

69 / 102 page

EM77950

BB Controller

Product Specification (V1.0) 10.09.2007

• 61

(This specification is subject to change without further notice)

8.3.14

System Status Register (SSR)

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SSR

TX_UF

BIT_ERROR

LOCK

TX EMPTY

LOCKED

CRC ERROR

This register is a read-only register.

This register provides status information to the MCU concerning the communication

line and the data transfer. Bits 1, 2, 3 can trigger the interrupt if enabled in the IER. Bits

0, 5 and 6 are set by H/W and cleared automatically after the MCU reads the register.

Bits 1~4 are set and cleared by H/W.

Bit 0:

CRC_ERROR

This flag indicates a CRC Error in the packet. The CRC Block sets this flag at

the end of each received packet according to the CRC calculation result. BB

compares the calculated CRC and the received CRC. When these values

differ, the flag goes high.

The flag is cleared only after the MCU reads the SSR register. If the MCU does

not read the SSR register, this flag remains “1”.

Bit 1:

LOCKED

This flag indicates that a packet is being received.

Bit 1 is set to Logic 1 whenever the system identifies a new incoming packet

(triggers LOCK IN interrupt). The bit will reset to Logic 0 when the packet ends

(triggers LOCK OUT interrupt) or when one of the IDs fails (NET or BYTE).

This indicator is important whenever we want to switch to transmit mode

because it can tell us that the line is busy and that in most cases the

transmission will not succeed. The Lock triggers interrupt for every change in

the bit status.

Bit 2:

TX_EMPTY

This bit is the Transmitter Empty flag. When this bit is high the system is

available for loading the next packet for transmission and BB is in receive

mode. When the flag is low, BB is in the middle of a packet transmission.

When transmitting few successive packets, the MCU should wait to the end of

a packet before it reloads the TX_FIFO with the next packet.

Bit 3:

Carrier Sense detection bit

When this bit is high, the system has identified a structure of packet

transmission in the air according to CSR.

When low, no carrier has been detected. This bit is only valid in receive mode.

The conditions for setting or clearing this flag are determined in the CS register.

When LOCKED is high, then CS is meaningless.

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