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EM77950 Datasheet(PDF) 86 Page - ELAN Microelectronics Corp |
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EM77950 Datasheet(HTML) 86 Page - ELAN Microelectronics Corp |
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86 / 102 page ![]() EM77950 BB Controller 78 • Product Specification (V1.0) 10.09.2007 (This specification is subject to change without further notice) 11.3 PWM Programming Procedures/Steps (1) Load PRDX with the PWMX period. (2) Load DTX with the PWMX Duty Cycle. (3) Enable the interrupt function by setting PWMXIE in the INTE register, if required. (4) Set the PWM pin as output by setting PWMCR.S_PWMX. (5) Enable the PWM function by setting PWMXE bit in the PRIE register. (6) Write the desired new duty to DTX before TMRX is equal to PRDX, then this new DTX will be latched into DLX if various duty cycle is required for the next PWMX operation. (7) Clear PWMXE bit and write the desired new period to PRDX, then enable it again if various periods are required for the next PWMX operation. (8) Clear the PWMXIF before the next operation if interrupt PWMXIE is employed. 12 Interrupts 12.1 Introduction The EM77950 has 15 interrupt sources. By priority, these interrupts are classified into two levels, namely; peripherals and base band, as described in the following: The interrupt status registers record the interrupt requests in the corresponding control bits in the interrupt control registers. The global interrupt (GIE) is enabled by the ENI instruction and is disabled by the DISI instruction. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine to avoid recursive interrupts. The flags in the Interrupt Status Register are set regardless of the status of their corresponding mask bits or the execution of DISI. Note that the logic AND of an interrupt flag and its corresponding interrupt control bit is 1 which makes the program counter point to the right interrupt vector. Refer to Fig. 12-1. The RETI instruction ends the interrupt routine and enables the global interrupt (the execution of ENI). Before the interrupt subroutine is executed, the contents of ACC, SR and ROMPS will be saved by the hardware. After the interrupt service routine is finished, ACC, SR and ROMPS will be pushed back. |
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