EM77950 datasheet(65/102 Pages) EMC

65 / 102 page

EM77950

BB Controller

Product Specification (V1.0) 10.09.2007

• 57

(This specification is subject to change without further notice)

8.3.7 System Control Register 3 (SCR3)

This register is a read and a write register.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SCR3

LOW

MODE

ZERO

DISCH

CNT 2

ZERO

DISCH

CNT 1

ZERO

DISCH

CNT 0

ZERO

DISCH.

CAP DIS

PERIOD

EN CAP

DISCH.

Bit 1:

EN_CAP_DISCH

Enables/disables capacitor discharge mechanism after each received packet:

: Disables discharge.

: Enables discharge.

This bit overrides Bit 3.

Bit 2:

CAP_DIS_PERIOD

Determines the capacitor discharge duration:

: The pulse width is 36 clocks, (3

μsec at 12 MHz clock).

: The pulse width is 72 clocks, (3

μsec at 24 MHz clock).

Bit 3:

EN_ZERO_DISCH

Enables/disables zero counter mechanism for capacitor discharge:

: Disables discharge

: Enables discharge

Bits 4-6:

ZERO_DISCH_CNT [0:2]

Determine the number of zero bits that will trigger a capacitor discharge by the

zero counter mechanism.

ZERO DISCH

CNT 0

ZERO DISCH

CNT 1

ZERO DISCH

CNT 2

Number of Zeros

EM77950 Datasheet(PDF) 65 Page - ELAN Microelectronics Corp

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