EM77950 datasheet(59/102 Pages) EMC

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EM77950

BB Controller

Product Specification (V1.0) 10.09.2007

• 51

(This specification is subject to change without further notice)

Window

1usec

2 * 1usec

1usec

DATA_IO

Signal

(0)

ONE_CNT=0

ZERO_CNT=1

(1)

ONE_CNT=1

ZERO_CNT=0

(2)

ONE_CNT=1

ZERO_CNT=1

(3)

ONE_CNT=2

ZERO_CNT=0

(4)

ONE_CNT=2

ZERO_CNT=0

(5)

ONE_CNT=2

ZERO_CNT=1

(6)

ONE_CNT=1

ZERO_CNT=0

Fig. 8-4 Carrier-Sense Example

In the example shown in Figure 8-2, at time (1) a new “1” bit is received after a “0” bit

was received. Thus, ONE_CNT equals 1 and ZERO_CNT is reset to 0. At time (2), a

zero bit is received, so the ZERO_CNT is incremented. At time (3), a “1” is received

after a “0” bit that was received before it. Thus ONE_CNT is incremented and

ZERO_CNT is reset. At time (4) a “1” bit is received after a “1” bit, thus, there is no

change in any counter. At time (6) a “1” bit is received out of the allowed window, so

ONE_CNT is reset to 1.

The CSR register is used to configure the carrier-sense algorithm sensitivity. The CSR

The CSR also determines the number of successive “0” bits that reset the carrier-sense

state machine.

In SSR register, bit CS notifies whether a carrier was identified. Carrier-sense can also

be used as an interrupt. When CS in SSR goes from ‘1’ to ‘0’ i.e. the transmission has

stopped, a CS interrupt is invoked (if enabled in IER). The purpose of this interrupt is to

inform the MCU that the channel is free again.

If the BB identifies a packet, the carrier-sense algorithm halts. When the BB is in RX

mode and the LOCK flag in SSR is “0”, the CS mechanism is working. When the LOCK

flag in SSR is “1”, the CS mechanism is not working, since the CS flag does not add any

information because a Preamble was identified already. After a Preamble was

identified the CS in SSR equals ‘1’.

8.2.13

Receiver Reference Capacitor Discharge

BB implements two independent mechanisms for receiver capacitor discharge:

At the end of each received packet.

Zero counter.

Mechanism 1 is enabled/disabled by bit EN_CAP_DISCH in SCR3.

Mechanism 2 is enabled/disabled by bit EN_ZERO_DISCH in SCR3.

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