EM77950 datasheet(93/102 Pages) EMC

93 / 102 page

EM77950

BB Controller

Product Specification (V1.0) 10.09.2007

• 85

(This specification is subject to change without further notice)

15.4

Wake-up Procedure on Power-on Reset

Power-on Voltage Detector (POVD) will allow the VDD whose value is over the default

threshold voltage (2.0 V for the EM77950) to enter the IC, and the SST delay starts.

The following three cases may be taken into consideration:

(1) /RESET pin goes high with VDD at the same time. In hardware, this pin and VDD

are tied together. The internal reset will remain low until the SST delay is over.

(2) /RESET pin goes high during the SST delay. It is similar to Case 1. The IC will

start to operate when the SST delay is over.

/RESET pin goes high after an SST delay. The EM77950 will start program execution

immediately

16 Oscillators

16.1

Introduction

The EM77950 provides three main oscillators: One high frequency crystal oscillator

(connected to OSCI and OSCO), internal RC, and four PLL (Phase Lock Loop) outputs.

Versatile combinations of oscillation are provided for a wide range of applications.

On-chip clock sources can be either dual clocks or single clock.

16.2

Clock Signal Distribution

FRCC.FRCCS

MCU Kernel

8 bit ADC

16 bit PWM

8 bit TCC

WDT

6MHz

IRC CLK

PLL

(Power Down)

BYP

SYS_CLK 0/1=0

& RF_CLK 0/1=0

SYS_CLK 0/1

TCCC.TCCS0

SR.GREEN

SYS_NCLK

SYS_ICLK

SPI

RF-BB

RF_CLK 0/1

16 bit FRC

Fig. 16 Clock Tours

EM77950 Datasheet(PDF) 93 Page - ELAN Microelectronics Corp

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