EM77950 datasheet(91/102 Pages) EMC

91 / 102 page

EM77950

BB Controller

Product Specification (V1.0) 10.09.2007

• 83

(This specification is subject to change without further notice)

14.3.3

FRC Programming Procedures/Steps

(1) Load LFRCB with the FRC overflow period low byte.

(2) Load HFRC with the TCC overflow period high byte. Then LFRC will load with the

LFRCB automatically.

(3) Enable interrupt function by setting FRCOE in the INTE register, if required.

(4) Enable FRC function by setting FRCE bit in the PRIE register.

(5) Wait for either the interrupt flag to be set (FRCOF) or the FRC interrupt to occur.

(6) An access of low byte of a 16-bit counter receives the count value at the moment of

the read. However, the contents of low byte will transfer to the buffer, the LFRCB

unchanged until the corresponding low byte is read.

(7) The following formula describes how to calculate the FRC overflow period:

()

⎟

⎠

⎞

⎜

⎝

⎛

−

ClockSourc

LFRC

HFRC

Timer

FRC

10000

where Clock Source = Fosc or IRC

15 Reset and Wake up

15.1

Reset

A reset can be caused by one of the following:

(1) Power-on reset

(2) /RESET pin input "low", or

(3) Watchdog timer time-out (if enabled)

The device will remain in a reset condition for a period of 8-bit external RC ripple

counter (one oscillator start-up timer period) after the reset is detected. The initial

Address is 000h.

15.2

The Status of RST, T, and P of the STATUS Register

A reset condition can be caused by the following events:

(1) A power-on condition (external);

(2) A high-low-high pulse on the /RESET pin (external); and

(3) Watchdog timer time-out (internal).

The values of bits RST, T and P, listed in Table 17.1 can be used to check how the

processor wakes up.

EM77950 Datasheet(PDF) 91 Page - ELAN Microelectronics Corp

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