SH7616 datasheet(153/935 Pages) RENESAS

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Section 4 Exception Handling

Rev. 2.00 Mar 09, 2006 page 127 of 906

REJ09B0292-0200

4.1.2

Exception Handling Operations

Exception handling sources are detected, and exception handling started, according to the timing

shown in table 4.2.

Table 4.2

Timing of Exception Source Detection and Start of Exception Handling

Exception Source

Timing of Source Detection and Start of Handling

Reset

Power-on reset

Starts when the NMI pin is high and the

RES pin changes from

low to high

Manual reset

Starts when the NMI pin is low and the

RES pin changes from

low to high

Address error

Detected when instruction is decoded and starts when the

previous executing instruction finishes executing

Interrupts

Detected when instruction is decoded and starts when the

previous executing instruction finishes executing

Instructions

Trap instruction

Starts from the execution of a TRAPA instruction

General illegal

instructions

Starts from the decoding of undefined code anytime except after

a delayed branch instruction (delay slot)

Illegal slot

instructions

Starts from the decoding of undefined code placed directly

following a delayed branch instruction (delay slot) or of an

instruction that rewrites the PC

When exception handling starts, the CPU operates as follows:

1. Exception handling triggered by reset

The initial values of the program counter (PC) and stack pointer (SP) are fetched from the

exception vector table (PC and SP are respectively addresses H'00000000 and H'00000004 for

a power-on reset and addresses H'00000008 and H'0000000C addresses for a manual reset).

See section 4.1.3, Exception Vector Table, for more information. 0 is then written to the vector

base register (VBR) and 1111 is written to the interrupt mask bits (I3–I0) of the status register

(SR). The program begins running from the PC address fetched from the exception vector

table.

2. Exception handling triggered by address errors, interrupts, and instructions

SR and PC are saved to the stack address indicated by R15. For interrupt exception handling,

the interrupt priority level is written to the SR’s interrupt mask bits (I3–I0). For address error

and instruction exception handling, the I3–I0 bits are not affected. The start address is then

fetched from the exception vector table and the program begins running from that address.

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